For example, a differential amplifier circuit in which a first current control circuit and a second current control circuit are provided for one of differential transistors forming a pair and the other thereof and a gain compensation circuit including a capacitance and a resistance is provided between the sources of the differential transistors is disclosed in JP-A No. 2005-142633. While use of a field-effect transistor having a silicon-on-insulator (SOI) structure causes a reduction in gain in a high frequency band (AC kink effect)s due to a parasitic body resistance and a parasitic capacitance, use of a differential amplifier circuit as described above allows achievement of a nearly flat frequency characteristic even in a high frequency band.
Also, a receiver circuit in which a differential amplifier circuit including a gain compensation circuit similar to what is disclosed in JP-A No. 2005-142633 and an ordinary differential amplifier circuit including no such gain compensation circuit are coupled in a manner that these differential circuits share an input signal, an output signal, and a load resistance pair is disclosed in U.S. Patent Application Publication No. 2006/0181348. In this receiver circuit, individually controlling ON/OFF of the tail currents of these two types of differential circuits allows only either differential amplifier circuit to operate. Also, use of the common input terminal and output terminal allows selective use of the differential amplifier circuits according to the characteristic of the transmission line.
Further, a flip-flop circuit that includes a differential amplifier and a source follower circuit having one of the outputs of the differential amplifier as an input thereof and in which the source of the source follower circuit is coupled to a current source via a metal oxide semiconductor (MOS) transistor having the other output of the differential amplifier as an input thereof is disclosed in JP-A No. 2003-283309. This differential amplifier has a three-stage structure in which a MOS transistor for data input, a MOS transistor for clock input, and a current source are coupled from a high potential power supply toward a low potential power supply. Such a configuration sufficiently secures the output current of the source follower circuit, allowing the flip-flop circuit to operate at a higher speed.